APPLICATION NOTE
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
Introduction
This application note provides an example of transferring data to on-chip peripheral modules with the direct memory
access controller (DMAC) of the SH7263/SH7203.
Target Device
SH7263/SH7203
Contents
1. Introduction ....................................................................................................................................... 2
2. Description of Sample Application.................................................................................................... 3
3. Sample Program............................................................................................................................... 9
4. Documents for Reference............................................................................................................... 15
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Data Transfer to On-chip Peripheral Modules with DMAC
2. Description of Sample Application
In this sample application, the DMAC and on-chip peripheral module requests are used to transfer data from external
memory to the SCIF.
2.1
Operational Overview of Modules Used
When a DMA transfer request is made, the DMAC starts to transfer data in accordance with the priority order of
channels, and continues the transfer operation until the transfer end condition is met. Transfer requests for the DMAC
are of three kinds: auto requests, external requests, and on-chip peripheral module requests. The bus mode is selectable
as burst mode or cycle-stealing mode.
An overview of the DMAC is given in table 1. Also, a block diagram of the DMAC is shown in figure 1.
Table 1 Overview of DMAC
Item
Description
Number of channels
8 (CH0 to CH7)
Only 4 (CH0 to CH3) can receive external requests.
Address space
4 Gbytes
Length of transfer data Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword × 4)
Maximum transfer
16,777,216 (24 bits) transfers
count
Address mode
Single address mode and dual address mode
Transfer request
Auto request, external request, and on-chip peripheral module request
•
SH7203/SH7263
(SCIF: 8 sources, I2C3: 8 sources, ADC: 1 source, MTU2: 5 sources, CMT: 2
sources, USB: 2 sources, FLCTL: 2 sources, RCAN-TL1: 2 sources, SSI: 4
sources, SSU: 4 sources)
•
SH7263
(SRC: 2 sources, ROM-DEC: 1 source, SDHI: 2 sources)
Bus mode
Cycle-stealing mode and burst mode
Priority level
Interrupt request
Channel priority fixed mode and round-robin mode
An interrupt request to the CPU is made when half or all of a transfer process is
completed.
External request
detection
DREQ input low/high level detection, rising/falling edge detection
Transfer request
acknowledge
signal/transfer end
signal
Active levels for DACK and TEND can be set independently
Note: For details on the DMAC, refer to the section on the direct memory access controller in the
SH7263/SH7203 Group Hardware Manual.
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DMAC module
RDMATCR_n
On-chip
memory
Iteration
control
DMATCR_n
RSAR_n
SAR_n
On-chip
peripheral
module
Register
control
RDAR_n
DAR_n
Start-up
control
DMA transfer
request signal
CHCR_n
DMAOR
DMA transfer acknowledge signal
Request
priority
control
HEIn
DEIn
Interrupt controller
DMARS0 to DMARS3
External ROM
Bus
interface
External RAM
External device
(memory mapped)
Bus state
controller
External device
(with acknowledge)
DREQ0 to DREQ3
DACK0 to DACK3,
TEND0, TEND1
[Legend]
RDMATCR: DMA reload transfer count register
DMATCR: DMA transfer count register
CHCR:
DMA channel control register
DMA operation register
DMAOR:
RSAR:
SAR:
DMA reload source address register
DMA source address register
DMARS0 to DMARS3: DMA extension resource selectors 0 to 3
HEIn:
DMA transfer half-end interrupt request to the CPU
DMA transfer end interrupt request to the CPU
0, 1, 2, 3, 4, 5, 6, 7
RDAR:
DAR:
DMA reload destination address register DEIn:
DMA destination address register n:
Figure 1 Block Diagram of DMAC
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2.2
Procedure for Setting Used Modules
This section describes the procedure for making initial settings when the DMAC is to be used to transfer data from
memory to on-chip peripheral modules. On-chip peripheral module requests are used for transfer requests. A flowchart
of DMAC initialization is shown in figure 2. For details on registers, refer to the SH7263/SH7203 Group Hardware
Manual.
• Enabling clock supply to the DMAC (STBCR2)
Clear the MSTP8 (module stop 8) bit to 0
[Function] Clock supply to the DMAC
[1]
[2]
START
• Disabling DMA transfer (CHCRn)
Clear the DE (DMA enable) bit to 0
[Function] Disable DMA transfer
Set standby control register 2
(STBCR2)
[1]
[2]
[3]
[4]
• Setting DMA transfer source address (SARn)
[Function] Specify DMA transfer source address
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Set DMA channel control register
(CHCRn)
• Setting DMA transfer source reload address (RSARn)
[Function]
Specify DMA transfer source address to be reloaded
• Setting DMA transfer destination address (DARn)
[Function] Specify DMA transfer destination address
Set DMA source address control
register (SARn)
• Setting DMA transfer destination reload address (RDARn)
[Function] Specify DMA transfer destination address to be reloaded
• Setting the DMA transfer count (DMATCRn)
[Function] Set the DMA transfer count
Set DMA reload source
address register (RSARn)
• Setting the DMA transfer reload count (RDMATCRn)
[Function] Set the DMA transfer count to be reloaded
• Setting the DMA transfer mode (CHCRn)
Set the TC (transfer count mode) bit
[Function] "0": Transfer data once for each transfer request
(When the SCIF or IIC3 is selected as the transfer
request source)
Set DMA destination address
register (DARn)
[5]
[6]
"1": Transfer data for the count specified in DMATCRn for
each transfer requests
Set DMA reload destination
address register (RDARn)
Set the RLDSAR (SAR reload function enable/disable) bit
[Function] Enables/disables reload function to SAR and DMATCR
Set the RLDDAR (DAR reload function enable/disable) bit
[Function] Enables/disables reload function to DAR and DMATCR
Set the DM (destination address mode) bits
[Function] Select whether the DMA transfer destination address is
incremented or decremented
Fix/increment/decrement the DMA transfer destination address
Set the SM (source address mode) bits
[Function] Select whether the DMA transfer source address is
incremented or decremented
Fix/increment/decrement the DMA transfer source address
Set the RS (resource select) bits to B'1000.
[Function] Select DMA extension resource selector (DMA transfer
request source)
Set the TB (transfer bus mode) bit
[Function] Select a DMA transfer bus mode.
Cycle-stealing mode/burst mode
Set DMA transfer count register
(DMATCRn)
[7]
[8]
Set DMA reload transfer
count register (RDMATCRn)
Set DMA channel control register
(CHCRn)
[9]
Note: When TC is set to 0, select cycle-stealing mode
Set the TS (transfer size) bits
[Function] Specify the DMA transfer size
Set the IE (interrupt enable) bit
[Function] Enable/disable interrupt requests
Set DMA extension resource selector
registers (DMARS0 to DMARS3)
[10]
• Specifying settings for DMA transfer requests from on-chip peripheral
modules (DMARS0 to DMARS3)
[Function] Select the DMA transfer request source
SCIF, IIC3, A/D converter, MTU2, or CMT
[10]
[11]
Set DMA operation register
(DMAORn)
[11]
[12]
• Setting the DMA operation register (DMAOR)
Read from the AE (address error flag) bit and then clear it to 0
[Function] Clear the address error flag
Read from the NMIF (NMI flag) bit and then clear it to 0
[Function] Clear the NMI flag
Set the DME (DMA master enable) bit to 1
Set DMA channel control register
(CHCRn)
[Function] Enable DMA transfer on all the channels
END
• Enablling DMA transfer (CHCRn)
Set the DE (DMA enable) bit to 1
[Function] Start DMA transfer
[12]
Figure 2 Flowchart of Initializing DMAC
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2.3
Operation of Sample Program
In this sample program, SCIF transmit FIFO data empty transfer requests are made to activate DMAC channel 1, and to
transfer data from external memory to the transmit FIFO data register (SCFTDR) on SCIF channel 0. The data written
to SCFTDR on SCIF channel 0 are transmitted in UART mode. An operation timing of the sample program is shown in
figure 3.
DMA transfer using SCIF transmit FIFO data empty transfer requests
(Timing of requesting data transfer from external memory to the SCIF transmit FIFO data register: a
transfer request is made when the number of data in transmit FIFO becomes 0)
One data
transfer
One data
transfer
One data
transfer
One data
transfer
Read
Read
Read
Read
DMAC1
Write
Write
Internal signal
Write
Internal signal
Write
Bus
mastership
Internal signal
CPU
Write to SCIF transmit FIFO data register (SCFTDR)
Write
Write
Write
Write
Internal bus
Read
Read
Read
Read
External bus
DMA transfer request
(When the DMA master
enable bit is 1)
SCIF transmit FIFO data empty transfer request (on-chip peripheral request)
H'28 H'27
DMA transfer count
register (DMATCR)
H'29
H'00
Transfer end flag (TE)
[Legend]
: DMA request acknowledge
Figure 3 Operation Timing of Sample Application
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2.4
Processing Procedure of Sample Program
In this sample program, character string data stored in external memory are transferred by DMA to the transmit FIFO
data register (SCFTDR) on SCIF channel 0, and then are transmitted in UART mode.
The register settings for the sample program are listed in table 2. The macro definitions used in this sample program are
also listed in table 3. A flowchart of the sample program is illustrated in figure 4.
Table 2 Register Settings for Sample Program
Register Name
Address
Setting Value
Description
Standby control
H'FFFE 0018
H'00
MSTP8 = "0": DMAC operates
register 2 (STBCR2)
DMA channel control
register 1 (CHCR1)
H'FFFE 101C
H'0000 0000
H'0000 1800
DE = "0": Disables DMA transfer
TC = "0": Transfers data once for each
DMA transfer request
RLDSAE = "0":
Disables SAR reload function
RLDDAR = "0":
Disables DAR reload function
DM = "B'00": Fixes destination address
SM = "B'01": Increments source address
RS = "B'1000": Extension resource selector
TB = "0": Cycle-stealing mode
TS = "B'00": Byte transfer
IE = "0": Disables interrupt request
H'0000 1801
DE = "1": Enables DMA transfer
DMA source address
register_1 (SAR1)
H'FFFE 1010
H'FFFE 1014
H'FFFE 1018
Address where
character string
data are stored
Start address of transfer source:
Start address of character string stored in
external memory
Start address of transfer destination:
Address of the SCIF transmit FIFO data
register_1 (SCFTDR_1)
DMA destination
address register_1
(DAR1)
H'FFFE 800C
DMA transfer count
register_1 (DMATCR1)
Number of
character string
data
Transfer count: the number of character
string data
DMA operation register H'FFFE 1200
(DMAOR)
H'0001
DME = "1": Enables DMA transfer on all the
channels
DMA extension
resource selector
(DMARS0)
H'FFFE 1300
H'0081
MID = "B'100000"
RID = "B'01"
Set to SCIF_0 transmit FIFO data empty
transfer request
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Table 3 Macro Definitions Used in Sample Program
Macro Definition
Setting Value
H'0000
H'0001
H'0002
H'0003
Description
DMA_SIZE_BYTE
DMA_SIZE_WORD
DMA_SIZE_LONG
DMA_SIZE_LONGx4
DMA_INT_DISABLE
DMA_INT_ENABLE
Byte transfer
Word transfer
Longword transfer
16-byte transfer
DMA transfer end interrupt disabled
DMA transfer end interrupt enabled
H'0000
H'0010
START
Initialize DMAC/enable transfer
io_init_dma1()
Initialize SCIF/enable
transmission and transmission
interrupts
io_init_scif()
No
DMA transfer
completed?
Yes
END
Figure 4 Flowchart of Sample Program
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3. Sample Program
1. Sample Program Listing "main.c" (1)
1 /*""FILE COMMENT""**************************************************************
2 *
3 *
4 *
5 *
6 *
7 *
8 *
9 *
10*
11*
12*
13*
14*
15*
16*
17*
18*
19*
20*
21*
22*
23*
24*
25*
26*
System Name: SH7203 Sample Program
File Name : main.c
Contents
Version
Model
: Data transfer to on-chip peripheral modules with DMAC
: 1.00.00
: M3A-HS30
CPU
: SH7203
Compiler
note
: SHC9.1.1.0
: Sample program for transferring data from the SCIF by DMAC1
<CAUTION>
This sample program is for reference
and its operation is not guaranteed.
Customers should use this sample program for technical reference
in software development.
The information described here may contain technical inaccuracies or
typographical errors. Renesas Technology Corporation and Renesas Solutions
assume no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Copyright(C) 2007 Renesas Technology Corp. All Rights Reserved
AND Renesas Solutions Corp. All Rights Reserved
history
: 2007.12.27 ver.1.00.00
27*""FILE COMMENT END""*********************************************************/
28#include <string.h>
29#include "iodefine.h"
30
/* iodefine.h is automatically created by HEW */
31/* ==== Macro declaration ==== */
32/* ==== DMAC Settings ==== */
33#define DMA_SIZE_BYTE
34#define DMA_SIZE_WORD
35#define DMA_SIZE_LONG
36#define DMA_SIZE_LONGx4
37#define DMA_INT_DISABLE
38#define DMA_INT_ENABLE
39#define DMA_INT
0x0000u
0x0001u
0x0002u
0x0003u
0x0000u
0x0010u
(DMA_INT_ENABLE >> 4u)
40
41/* ==== Prototype declaration ==== */
42void main(void);
43void io_init_dma1(void *src, void *dst, size_t size, unsigned int mode);
44void io_dma1_stop(void);
45void io_init_scif0(int);
46
47/* ==== Type declaration ==== */
48/* SCIF baud rate setting */
49typedef struct {
50
51
unsigned char scbrr;
unsigned short scsmr;
52} SH7203_BAUD_SET;
53
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2. Sample Program Listing "main.c" (2)
54 /* ---- Values for baud rate specification ---- */
55 enum{
56
57
58
CBR_1200,
CBR_2400,
CBR_4800,
CBR_9600,
CBR_19200,
CBR_31250,
CBR_38400,
CBR_57600,
CBR_115200
59
60
61
62
63
64
65 };
66
67 /* ==== Table of register setting values ==== */
68 static SH7203_BAUD_SET scif_baud[] = {
69
70
{214, 1},
{106, 1},
{214, 0},
{106, 0},
{ 53, 0},
{ 32, 0},
{ 26, 0},
{ 17, 0},
{ 8, 0}
/* 1200bps (-0.07%) */
/* 2400bps ( 0.39%) */
/* 4800bps (-0.07%) */
/* 9600bps ( 0.39%) */
/* 19200bps (-0.54%) */
/* 31250bps ( 0.00%) */
/* 38400bps (-0.54%) */
/* 57600bps (-0.54%) */
/*115200bps (-0.54%) */
71
72
73
74
75
76
77
78 };
79 /* Character string to be transmitted */
80 const signed char data[] = "SCIF request DMAC Sample Software SH7203.¥r¥n";
81
82 /*""FUNC COMMENT""*******************************************************
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
* Outline
*-----------------------------------------------------------------------
* Include : #include <string.h>
*-----------------------------------------------------------------------
* Declaration : void main(void);
*-----------------------------------------------------------------------
: Sample Program Main (UART transmission with use of DMAC)
* Function
*
*
: The character string data stored in external memory is DMA transferred
: to the SCIF transmit FIFO data register. The DMAC is activated
: by an SCIF transmit interrupt request.
*-----------------------------------------------------------------------
* Argument : void
*-----------------------------------------------------------------------
* Return Value : void
*-----------------------------------------------------------------------
* Notice
*""FUNC COMMENT END""***************************************************/
:
99 void main(void)
100 {
101
102
103
104
105
106
/* ==== Enabling DMAC initialization/transfer ==== */
io_init_dma1(data, (void *)&SCIF0.SCFTDR.BYTE ,sizeof(data),
DMA_SIZE_BYTE | DMA_INT_DISABLE);
/* On-chip peripheral module request (SCIF transmit interrupt request) */
/* Data transfer from external memory to SCIF transmit */
/* Data transfer to data registers */
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3. Sample Program Listing "main.c" (3)
107
108
109
110
111
112
113
114
115
116
117
/* ==== Enabling SCIF0 initialization/transfer ==== */
io_init_scif0(CBR_115200);
/* Communication mode :UART mode */
/* Bit rate:115.2Kbps */
/* TXI interrupt is generated when data in transmit FIFO is one byte */
/* ==== Disabling DMA transfer ==== */
io_dma1_stop();
while(1){
/* Program end */
}
}
118 /*""FUNC COMMENT""*******************************************************
119 * Outline : Initialization for DATA transfer between memory areas with DMAC
120 *-----------------------------------------------------------------------
121 * Include : #include "iodefine.h"
122 *-----------------------------------------------------------------------
123 * Declaration : io_init_dma1(void *src, void *dst, size_t size, int mode);
124 *-----------------------------------------------------------------------
125 * Function
126 *
: The DMAC transfers the amount of data specified by “size”.
: from the source address “src” to the destination address “dst.”
: Transfer is performed using requests from the SCIF1.
127 *
128 *
: “mode” is specified for transfer size and interrupt used/not used.
129 *-----------------------------------------------------------------------
130 * Argument
131 *
132 *
: void *src
: void *dst
: size_t size
: Source address
: Destination address
: Transfer size (byte)
133 *
: unsigned int mode: Transfer mode, specifies the following with logical OR.
134 *
135 *
:
:
:
:
:
:
DMA_SIZE_BYTE (0x0000) Byte transfer
DMA_SIZE_WORD (0x0001) Word transfer
136 *
137 *
138 *
DMA_SIZE_LONG (0x0002) Longword transfer
DMA_SIZE_LONGx4(0x0003) 16-byte transfer
DMA_INT_DISABLE(0x0000) DMA transfer end interrupt disabled
DMA_INT_ENABLE (0x0010) DMA transfer end interrupt disabled
139 *
140 *-----------------------------------------------------------------------
141 * Return Value: void
142 *-----------------------------------------------------------------------
143 * Notice
144 *
: Operation is not guaranteed when the alignment of the source/destination.
: address is inconsistent.
145 *
: When interrupts are used, interrupt routines must be registered.
146 *""FUNC COMMENT END""***************************************************/
147 void io_init_dma1(void *src, void *dst, size_t size, unsigned int mode)
148 {
149
150
151
152
153
154
155
156
157
158
159
160
unsigned int ts;
unsigned long ie;
ts = mode & 0x3u;
ie = (mode & 0x00f0u ) >> 4u;
/* ====Setting standby control register 2(STBCR2) ==== */
CPG.STBCR2.BIT.MSTP8 = 0x0;
/* Cancel DMAC module top mode */
/* ---- Setting DMA channel control register ---- */
DMAC.CHCR1.BIT.DE = 0ul;
/* Disable DMA transfer */
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4. Sample Program Listing "main.c" (4)
161
162
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197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
/* ----Setting DMA source address register---- */
DMAC.SAR1.LONG = (unsigned long)src;
/* ----Setting DMA reload source address register---- */
DMAC.RSAR1.LONG = (unsigned long)src;
/* ----Setting DMA destination address register---- */
DMAC.DAR1.LONG = (unsigned long)dst;
/* ----Setting DMA reload destination address register---- */
DMAC.RDAR1.LONG = (unsigned long)dst;
/* ----Setting DMA transfer count register---- */
/* ----Setting DMA reload transfer count register---- */
switch(ts){
case DMA_SIZE_BYTE:
DMAC.DMATCR0.LONG = size;
DMAC.RDMATCR0.LONG = size;
break;
/* Specify transfer count (1/1) */
case DMA_SIZE_WORD:
DMAC.DMATCR0.LONG = size >> 1u;
DMAC.RDMATCR0.LONG = size >> 1u;
break;
case DMA_SIZE_LONG:
DMAC.DMATCR0.LONG = size >> 2u;
DMAC.RDMATCR0.LONG = size >> 2u;
break;
case DMA_SIZE_LONGx4:
DMAC.DMATCR0.LONG = size >> 4u;
DMAC.RDMATCR0.LONG = size >> 4u;
break;
/* Specify transfer count (1/2) */
/* Specify transfer count (1/4) */
/* Specify transfer count (1/16) */
default:
break;
}
/* ----Setting DMA channel control register---- */
DMAC.CHCR1.LONG = 0x00001800ul | (ts << 3u) | (ie << 2u) ;
/*
bit31
bit30
bit29
bit28
: TC DMATCR transfer0---------
: reserve 0
Transfer once
: RLDSAR OFF : 0-------------
: RLDDAR OFF : 0-------------
Disable SAR reload function
Disable DAR reload function
bit27-24 : reserve 0
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
: DO over run0 : 0----------
: TL TEND low active : 0----
: reserve 0
Unused
Unused
: TEMASK : TE set mask : 0--
: HE :0---------------------
: HIE :0--------------------
: AM :0---------------------
: AL :0---------------------
Disable DMA transfer when TE bit is set
Unused
Unused
Unused
Unused
bit15-14 : DM1:0 DM0:0---------------
bit13-12 : SM1:0 SM0:1---------------
Fix destination address
Increment source address
DMA extension resource selector
Unused
bit11-8
bit7
: RS : auto request : B'1000-
: DL : DREQ level : 0 -------
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5. Sample Program Listing "main.c" (5)
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238 }
bit6
bit5
bit4-3
bit2
bit1
bit0
: DS : DREQ select :0 Low level
Unused
: TB : cycle :0---------------
: TS : transfer size:B'00---
: IE : interrupt enable:0---
: TE : transfer end----------
: DE : DMA enable bit:0-----
Cycle-stealing mode
Byte transfer
Disable interrupt
DMA
*/
/* ----Setting DMA extension resource selector 0---- */
DMAC.DMARS0.BIT.CH1MID = 0x20;
DMAC.DMARS0.BIT.CH1RID = 0x01;
/* MID = SCIF0 */
/* RID = Transmission */
/* ----Setting DMA operation register---- */
DMAC.DMAOR.WORD &= 0xfff9u;
/* Clear AE,NMI bits
*/
if(DMAC.DMAOR.BIT.DME == 0ul){
DMAC.DMAOR.BIT.DME = 1ul;
}
/* Enable DMA transfer on all channels
*/
/* ----DMA transfer execution---- */
DMAC.CHCR1.BIT.DE = 1ul;
/* Enable DMA transfer
*/
239 /*""FUNC COMMENT""*******************************************************
240 * Outline : DMAC stop
241 *-----------------------------------------------------------------------
242 * Include : #include "iodefine.h"
243 *-----------------------------------------------------------------------
244 * Declaration : void io_dma1_stop(void);
245 *-----------------------------------------------------------------------
246 * Function: Detects the end of DMA transfer and disables DMA transfer
247 *-----------------------------------------------------------------------
248 * Argument: void
249 *-----------------------------------------------------------------------
250 * Return Value: void
251 *-----------------------------------------------------------------------
252 * Notice
:
253 *""FUNC COMMENT END""***************************************************/
254 void io_dma1_stop(void)
255 {
256
257
258
259
260
261
262
263 }
264
/* Detecting end of transfer */
while(DMAC.CHCR1.BIT.TE == 0ul){
/* Wait until the TE bit is set*/
}
/* ----Stopping DMA transfer---- */
DMAC.CHCR1.BIT.DE = 0ul;
/* Disable DMA1 transfer */
265 /*""FUNC COMMENT""*******************************************************
266 * Outline : Initial setting of SCIF0 as an asynchronous (UART) transmit module
267 *-----------------------------------------------------------------------
268 * Include : #include "iodefine.h"
269 *-----------------------------------------------------------------------
270 * Declaration : void io_init_scif0(int bps);
271 *-----------------------------------------------------------------------
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6. Sample Program Listing "main.c" (7)
272 * Function
: Initializes SCIF0
273 *
: Asynchronous (UART)/ 8 bits/ No parity/ 1 stop bit/ RTS/CTS disabled
274 *
275 *
: Baud rate is specified by argument bps
:
276 *-----------------------------------------------------------------------
277 * Argument: int bps : Value for baud rate specification
278 *-----------------------------------------------------------------------
279 * Return Value: void
280 *-----------------------------------------------------------------------
281 * Notice
282 *
: The baud rate setting values given in this program are those when
: the peripheral module clock (Pf) frequency is 33 MHz. If a different
: clock is used, the baud rate setting values must be changed.
283 *
284 *""FUNC COMMENT END""***************************************************/
285 void io_init_scif0(int bps)
286 {
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326 }
/* ====Power-down mode cancellation==== */
/* ----Setting standby control register 4 (STBCR4)---- */
CPG.STBCR4.BIT.MSTP47 = 0;
/* Start clock supply to SCIF0 */
/* ====SCIF0 initialization==== */
/* ----Setting serial control register (SCSCRi)---- */
SCIF0.SCSCR.WORD = 0x0000;
/* Stop transmission/reception by SCIF0 */
/* ----Setting FIFO control register (SCFCRi)---- */
SCIF0.SCFCR.BIT.TFRST = 1;
/* Reset transmit FIFO */
/* ----Setting serial control register (SCSCRi)---- */
SCIF0.SCSCR.BIT.CKE = 0x0; /* B'00: Internal clock */
/* ----Setting serial mode register (SCSMRi)---- */
SCIF0.SCSMR.WORD = scif_baud[bps].scsmr;
/* Communication mode 0: Asynchronous mode
*/
*/
/* Character length
/* Parity enable
/* Parity mode
0: 8-bit data
0: Disable addition and check */
0: Even parity
0: 1 stop bit
: Table value
*/
*/
*/
/* Stop bit length
/* Clock select
/* ----Setting bit rate register (SCBRRi)---- */
SCIF0.SCBRR.BYTE = scif_baud[bps].scbrr;
/* ----Setting FIFO control register (SCFCRi)---- */
SCIF0.SCFCR.WORD = 0x0030;
/* Transmit FIFO data count trigger
: Number of data bytes = 0*/
/* Modem control enable : Disabled */
/* Transmit FIFO data register reset : Disabled */
/* Loopback test : Disabled */
/* ====Setting pin function controller (PFC)==== */
PORT.PECRL1.BIT.PE1MD = 0x3; /* Switch to TxD0 pin */
/* ----Setting serial control register (SCSCRi) ---- */
SCIF0.SCSCR.BIT.TIE = 1;
SCIF0.SCSCR.BIT.TE = 1;
/* Enable SCIF0 transmit interrupt */
/* Enable SCIF0 transmission */
327 /* End of File */
REJ06B0734-0100/Rev.1.00
April 2008
Page 14 of 17
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
4. Documents for Reference
•
Software Manual
SH-2A, SH2A-FPU Software Manual
The most up-to-date version of this document is available on the Renesas Technology Website.
•
Hardware Manual
SH7203 Group Hardware Manual
SH7263 Group Hardware Manual
The most up-to-date version of this document is available on the Renesas Technology Website.
REJ06B0734-0100/Rev.1.00
April 2008
Page 15 of 17
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
Website and Support
Renesas Technology Website
Inquiries
Revision Record
Description
Rev.
Date
Page
Summary
1.00
Apr.17.08
—
First edition issued
All trademarks and registered trademarks are the property of their respective owners.
REJ06B0734-0100/Rev.1.00
April 2008
Page 16 of 17
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
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2008. Renesas Technology Corp., all rights reserved.
REJ06B0734-0100/Rev.1.00
April 2008
Page 17 of 17
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